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Results of Examination of Genesis Cartridges with SRAM

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This message was posted by Cryect, posted on December 17, 2001 at 15:56:37 coming from 128.220.194
Alright well I finally finished analyzing exactly how exactly the battery save SRAM works. From my research assuming the ROM use SRAM like its supposed to on the Genesis then everything below should be true.

128Kbits Max Needs to be switchable

Pin Connection of the 74HC00 from Shining Force
Pin 1 (1A) - Input from Edge B17 (CS)
Pin 2 (1B) - Input from Edge B17 (CS)
Pin 3 (1Y) - Output to Pin 4 & pin 9
Pin 4 (2A) - Input from Pin 3(1Y)
Pin 5 (2B) - Input from Edge B9 (A21)
Pin 6 (2Y) - Output to CS of SRAM
Pin 7 (GND)
Pin 8 (3Y) - Output to ROM (CS)
Pin 9 (3A) - Input from Pin 3(1Y)
Pin 10 (3B) - Output to Pin 11(4Y)
Pin 11 (4Y) - Output to Pin 10(3B)
Pin 12 (4A) - Input from Edge B9 (A21)
Pin 13 (4B) - Input from Edge B9 (A21)
Pin 14 (Vcc)

Equivlent Logic
CS of SRAM = -([-Edge B17(CS)]&&[Edge B9(A21)])
Logic Table
+--------------+
|CS |A21|Output|
| L | L | H |
| L | H | L |
| H | L | H |
| H | H | H |
+--------------+

CS of ROM = -([-Edge B17(CS)]&&[-Edge B9(A21)])
Logic Table
+--------------+
|CS |A21|Output|
| L | L | L |
| L | H | H |
| H | L | H |
| H | H | H |
+--------------+

You could get the same results using a 2 bit or 3 bit binary decoder.

ROM Size can not be larger than 24Mbits when using SRAM unless it breaks these rules or it's actually holds even more than 32Mbits and which the regions between 24Mbits-32Mbits will actually be accessing SRAM and same for any other area where A21 is High.

Now to finish designing my schematic now that I know this information.

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